1. Field of the Invention
The invention relates to an accounting means for tracking the flow of data between a peripheral storage device and main memory, and more particularly a data byte accounting system combining the economy and reliability of firmware with the high data transfer rates characteristic of hardware control.
2. Prior Art
Data processing systems wherein a plurality of system units are electrically coupled to a common communication bus for asynchronous intercommunication are disclosed in U.S. Pat. No. 3,993,981 and in U.S. application Ser. No. 643,439 filed Dec. 22, 1975, now U.S. Pat. No. 4,003,033 each assigned to the assignee of the present invention.
Prior data processing systems having the common bus architecture have relied solely on firmware control to accommodate data transfers between mass storage devices such as a disk and the common bus. With the incorporation of mass storage devices supplying data words at a rate of the order of ten times that of the prior transfer rates, a new control architecture was required. Further, the time penalties suffered in amending range counts and memory address data directly from a scratchpad memory could no longer be tolerated. Thus, the system data rates required a departure from the previous all firmware control architecture.
The present invention is directed to a system wherein system data control is shared between firmware and hardware in a manner to accommodate high data transfer rates.